An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

: This project describes in detail the process of designing and simulating CMOS Technology is used in a one-stage folded cascode operational amplifier (SFCOA) with the self-biasing scheme for the NMOS a stage of differential input is discussed. The design of the required circuits is done using the LTspice simulator. We will see that the simulation result approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation, then; two stage of (FCOA) technique with Miller compensation technique for the NMOS input have been employed. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applicable technique, which includes all of the design equations, has been fully stated in order to implement the circuit design for a particular specification. The parameter of Phase Margin (PM) and DC Gain are presented and discussed. Finally, a designed circuit based on NMOS input provide a 96 DC Gain has been performed.


METHOD 2.1. APPLIED METHODOLOGY AND SPECIFICATIONS
A-In milestone1, a (SFCOA) using 0.25µm CMOS technology with a self-biasing scheme for the NMOS differential input stage is designed using the LTspice simulator. Design is supposed to follow the given specifications: i) Power dissipation ≤ 2.5 mW ii) Open loop DC voltage gain, |Av0| ≥ 500 iii) Overdrive voltage, |VOD| = 0.3 V for all transistors excluding the input pair iv) Gate length, L = 2 µm for all transistors as shown in Figure 1.

Procedures (milestone1)
Following procedures are being implemented to design the required above circuit: [23][24][25][26][27][28] 1. Initially, naming of the different transistors of the main circuit and the self-biasing circuit is done with the given format. Then, as mentioned, the tail current is replaced with the help of a cascode current source. And all the bias voltages of the circuit are implemented with the help of high-swing cascode current mirror. The different values considered here for the given above specifications are mentioned in the Table 1:  Table 2) [29][30][31][32][33][34][35].

RESULTS AND DISCUSSION 3.1 OBSERVATIONS (milestone 1)
In the above results of operating point analysis, different nodal voltages and currents through the transistors can be observed and can be used to bring all the transistors in the saturation region. One can see that the values obtained are approximately similar to the values obtained using hand calculations for the given specifications. To make all the MOSFETs to be in saturation, the width of MBP1 has been changed to 28 µm from 37.037 µm (as per calculations) and the width of MBN1 has been changed to 7 µm from 9.662 µm (as per calculations) as shown in Figure 2. From the above figure, the range of Vin (ICMR) is obtained using the DC analysis of the above circuit.

TRANSIENT PLOTS FIGURE 4. -Transfer plot.
From the above plot, the gain of the circuit is obtained and it can be seen that it is nearly what has been desired in the milestone. Voltages of the differential input and single ended output are shown in different plot panes. Vo(pp) obtained is 105.63 mV for the given sine signal mentioned above.

THEORITICAL CALCULATONS OF (milestone 2)
This section shows you how to design a basic miller-compensated two-stage CMOS op amp. It also gives you the basic equations for op amps. where VOV = (VGS -Vtn ) for NMOS and VOV = (VSG -Vtp ) for PMOS, will be used in the paper as a whole. For a bulk MOSFET to work well at room temperature, VOV values of more than 200 mV are usually needed for strong inversion.
Step 1: The pole P2 should be placed 2.2 times higher than the Gain on the compensation capacitor Cc. The resulting need for the minimum value for Cc is as follows: Step 2: The estimation of the bias current is the next step in the design process. The slew rate specification provides us with: Slew rate: where Iss = I5 is the tail current.
Step 3: Taking into account the GB created by the dominant node, we have: Step 4: Figure 1 depicts the miller compensated two stage op amp with a reliable biasing circuit. It contains a high-swing cascode current mirror biasing circuit and two stages Op-Amp. The first stage typically consists of a differential amplifier with high gain. The common source amplifier typically satisfies the second stage's requirements and has a moderate gain.

FIGURE 8. -Gain and phase margin results
Simply put, the gain of the amplifier with infinite input resistance is the transconductance of the totally differential folded cascode op-amps. We have designed an op-amp with a gain more than 96 dB and a PM of: It serves as a gauge for the system's stability. The TSMC 0.25 µm Technology is used throughout the simulation and the minimum channel length of the transistors is set to 2 µm. The fully differential folded cascode op-amps were used in the simulation with 2.5 supply voltages at both NMOS input.

CONCLUSION
In conclusion, a (one-SFCOP) using 0.25 µm CMOS Technology with the self-biasing scheme for the NMOS differential input stage is designed. The procedures and hand calculations required for different transistors's widths and voltage biases are attached herewith. From the above simulation results, it can be notices that the circuit designed is performing as per desired. The high ICMR and high open-loop DC voltage gain is obtained. The range of Vin (ICMR) is obtained using the DC analysis of the above circuit. Using transient analysis, the gain of the circuit is obtained and it can be seen that it is nearly what has been desired in the milestone. Transfer function analysis verifies the gain obtained in the transient plot. From the netlist of the design, different nodal voltages and currents through the transistors can be observed and have been used to bring all the transistors in the saturation region. It can be seen that the values obtained are approximately similar to the values obtained using hand calculations for the given specifications. As we can see, with thorough design calculations, the design of single ended, two-stage operational amplifiers is described. According to simulation data, the op amp has a unity gain frequency of 1 kHz and an open loop DC gain of 96 dB.