Design A Combinational Circuit Consists of 10 Logic Gates Using Quartos

Abstract

Fault models are designed to forecast the expected behaviors (reaction) from the IC when faults are present, and this is what allows automated test pattern generation (ATPG) software to generate the test patterns. In order to identify these faults at every node in the circuit, the ATPG tool first consults the fault models to establish the patterns that will be necessary for doing so. In this article, ten logic gates are developed using the Quartos program to test for faults in a circuit, and the output waveform was simulated to determine the outcomes of the fault-free output using a variety of test patterns. This fault-free output is compared to the output when a fault injection occurs. It may then be determined if the various test patterns can be utilized to discover the fault in the simulation. The findings demonstrated that the fault can be discovered flawlessly.